1. Field of the Invention
The present invention relates to a method for manufacturing a thin-film transistor panel for use in an active matrix liquid crystal display device.
2. Description of the Related Art
A thin-film transistor panel (hereinafter called TFT panel) for used in an active matrix liquid crystal display device comprises a plurality of gate lines, plurality of thin-film transistors arranged to correspond to crossing points of these lines, and pixel electrodes connected to the plurality of thin-film transistors and arranged in a matrix form, which are formed on a transparent substrate, e.g., glass. An inverse stagger structure is used as a thin-film transistor.
More specifically, as shown in FIG. 16, the above conventional TFT panel is so constructed that a plurality of gate lines GL, a plurality of data lines DL, a plurality of thin-film transistors 2 of inverse stagger type, and a plurality of pixel electrodes 6 are formed on a transparent substrate 1 made of glass.
The thin-film transistors 2 of stagger type are structured such that the gate lines GL formed on the substrate 1 are used as gate electrodes, an i-type semiconductor layer is formed on a gate insulating film 3 covering the gate electrodes, and source and drain electrodes are formed on the i-type semiconductor layer 5 through an n-type semiconductor layer.
The gate insulating film 3 of the thin-film transistor 2 covers the gate lines GL, and is formed on the entire surface of the substrate 1. The gate insulating film 3 is a transparent film made of SiN (silicon nitride). The pixel electrodes 6 are formed on the gate insulating film 3. The pixel electrodes 6 are formed of a transparent conductive film made of ITO and the like, and one end of the respective pixel electrodes 6 is connected to the source electrode of the respective thin-film transistors 2.
The respective thin-film transistors 2 are covered with a protection insulating film 7, which is formed on the entire surface of the gate insulating film 3 and which is made of SiN. The respective data lines DL are formed on the protection insulating film 7. Each of data lines DL is electrically connected to the drain electrode of the thin-film transistor 2 through a contact hole formed in the film 7. It is noted that an opening through which each of the pixel electrodes 6 is exposed is formed in the protection insulating film 7.
Moreover, one end of each of the gate lines GL and one end of each of the data lines DL are led to the outside of a display area A (display area of the liquid crystal display device) in an outline shown by a two-dotted chain line. A large wide gate line terminal GLa is formed in a lead-through end of the respective gate lines GL, and a large wide data line terminal DLa is formed in a lead-through end of the respective data lines DL.
In the above-mentioned TFT panel, the terminals GLa of all gate lines GL are formed in the same side. In a TFT panel in which the number of gate lines is increased in order to improve resolution of the liquid crystal display device, as shown in FIG. 12, the terminals GLa of the gate lines GL are alternately formed to be opposed to each other so as to ensure a space between the respective gate line terminals. The gate line terminals GLa are exposed by forming an opening in the gate insulating film 3 and the projection insulating film 7, respectively.
Also, an overcoat insulating film (not shown) coating the thin-film transistors 2 and the data lines DL is formed on the surface of the above-mentioned TFT panel, and an orientation treatment is provided on its surface.
The active matrix liquid crystal display device is manufactured by bonding the above TFT panel is bonded to an opposing panel (not shown) through a frame-like sealing material enclosing the display area A, and sealing liquid crystal between both panels. The opposing panel is structured by that an opposite electrode (transparent electrode) is formed on a transparent substrate and an orientation treatment is provided thereon. The substrate 1 is a large-sized substrate from which can obtain a plurality of TFT panels. After manufacturing each TFT panel formed on the substrate 1 or after assembling the liquid crystal display device, the TFT panel assembly is separated into individual TFT panels by cutting the substrate 1 along a cutting line B shown by a one-dotted line in the figure.
Moreover, in the active matrix liquid crystal device, a storage capacitor is formed in the above TFT panel to correspond to the respective pixel electrodes 6 in order to reduce a variation of a potential held by the pixel electrodes during a non-selection period.
In FIG. 16, CL denotes a capacitor line constituting the above storage capacitor. The capacitor line CL is made of the same metal (Al, Al based-alloy, Ti, W, Mo, and the like) as that of the gate line GL, and is formed on the substrate 1. The capacitor line CL is formed to be parallel to the gate line GL, and opposed to one side peripheral portion of the respective pixel electrodes 6 arranged along the gate line GL.
The storage capacitor comprises the capacitor lines CL, pixel electrode 6, and gate insulating film 3 positioned therebetween. The storage capacitor stores an electrical charge applied to the pixel electrode 6 when the pixel electrode 6 is selected (when the thin-film transistor 2 is turned on). The potential of the pixel electrode 6 during the non-selection period is held by the storage capacitor.
Both ends of the capacitor line CL are led to the outside of display area A. The respective capacitor lines CL are connected in common at their both ends by earth lines EL. The earth lines EL are formed on the protection insulating film 7 to be parallel to the data lines DL, and connected to the end portion of the respective capacitor lines CL through a contact hole formed in the protection insulating film 7 and the gate insulating film 3. The earth lines EL are connected to a reference potential at their terminals ELa.
In the above-mentioned TFT panel, if there are defects, e.g., a pin hole, a crack, and the like, in the gate insulting films 3 and/or the protection insulating films 7, the gate lines GL and the source and drain electrodes are short-circuited at the thin-film transistor portion and layer short-circuit is generated between both lines at the crossing portion among the gate lines GL, the capacitor lines CL, and the data lines DL.
Due to this, according to the above TFT panel, the surfaces of the gate lines GL and the capacitor lines CL are oxidized, so that oxide films are formed on the surfaces of the gate lines GL and the capacitor lines CL. The surfaces of the gate lines GL and the capacitor lines CL are insulated by the oxide films, so that the generation of the layer short-circuits are prevented.
The TFT panel in which the oxide films are formed on the surfaces of the gate lines GL and the capacitor lines CL is manufactured by the following method.
First of all, a metal film, which is made of Al, an Al based-alloy containing Ti, Ta, and the like, Ta, W, Mo, and the like is formed on the substrate 1. The metal film is patterned, so that the gate lines GL and the capacitor lines CL, and oxide voltage-apply lines 8 are formed. The oxide voltage-apply lines 8 are formed on both sides (outside of cutting line B) of the portion to be used as a TFT panel, respectively. In this case, the respective gate lines GL are patterned to have a shape in which an extension is formed in the outer end of terminals GLa alternately formed to be opposed to each other. At the extension, right and left oxide voltage-apply lines 18 are alternately short-circuited. Also, the respective capacitor lines CL are patterned to have a shape in which one end portion is alternately extended to the opposite side. At the extended portion, right and left oxide voltage-apply lines 8 are alternately short-circuited.
Then, a voltage is applied to the gate lines GL and the capacitor lines CL from the oxide voltage-apply lines 8 and anodization is performed, thereby forming oxide films on the surfaces of the gate lines GL and the capacitor lines CL.
The anodization is performed as follows.
The substrate 1 is dipped in an electrolytic solution, and the gate lines GL and the capacitor lines CL are opposed to an opposed electrode (platinum electrode) in the electrolytic solution. These lines GL and CL are used as an anode and the opposed electrode is used as a cathode, and a voltage is applied between the electrodes. When the voltage is applied between the electrodes in the electrolytic solution, the chemical reaction takes place on the surfaces of the gate lines and capacity lines CL, and the surfaces are oxidized, so that the oxide films are formed on the surfaces of the liens GL and CL.
The anodization is performed in a state that a portion where the terminals GLa of the gate lines GL and the earth lines EL of the capacitor lines CL are respectively connected is covered with a resist mask. As a result, since the portion covered with the resist mask neither contacts the electrolytic solution nor is anodized, the gate line terminals GLa and the earth line connecting section of the capacitor lines CL are left as they are in a state that the surfaces thereof have conductivity.
Thereafter, the gate insulating film 3 is formed, and an i-type semiconductor layer and an n-type semiconductor layer, and source and drain electrodes are formed thereon, whereby the thin-film transistors 2 are formed by the well known method. Also, the pixel electrodes 6, data lines DL, and ground lines EL are formed, so that TFT panel is completed.
Under this state, the gate lines GL and the capacity lines CL are short-circuited to either right oxide voltage-apply line 8 or left oxide voltage-apply line 8 at their one end. However, the portion where the oxide voltage-apply line 8 is formed is separated from the TFT panel by cutting the substrate 1 along the cutting line B after the manufacture of the TFT panel or the assembly of the liquid crystal display device. At this time, the gate lines GL and the capacitor lines CL are cut and separated from the oxide voltage-apply lines 8.
According to the conventional TFT panel manufacturing method, since the anodization of the gate lines GL and the capacitor lines CL is performed by applying the voltage to the respective lines GL and CL from their one ends, if breaking of the capacitor lines CL occurs, the oxide film cannot be formed on the surface of the portion, which is beyond the broken portion of the capacitor line CL. As a result, layer short-circuit is often generated between the portion, which is beyond the broken portion of the capacitor line CL, and the data line DL.
The reason why the above problem occurs is as follows:
Although the voltage is applied to the portion between the end portion of the voltage-apply line of the capacitor line CL and the portion of the broken line when anodizing, no voltage can be applied to the portion, which is beyond the broken line. Due to this, the portion, which is beyond the broken line, cannot be anodized.
As mentioned above, if there are defects, e.g., a pin hole, a crack and the like in the gate insulating film and the protection insulating film, the data lines DL formed on the protection insulating film and the capacitor lines CL are short-circuited at the crossing portion with the portion, which is not covered with the oxide film of the capacitor line CL. As a result, the manufactured TFT panel becomes defective.
The breaking of the lines often occurs in not only the capacitor lines CL but also the gate lines GL. In this case, there can be formed a portion where the surface of the gate line GL is not anodized. Since the breaking of the gate lines GL results in a display detect of the liquid crystal display device, the TFT panel in which the gate lines are broken is regarded as a defective product regardless of the anodizing state of the gate lines GL.
In contrast, the capacitor liens CL are connected to the reference potential through the earth lines EL connected to both ends of the capacitor lines CL. Due to this, even if breaking of lines occurs in the capacitor lines CL, the electrical charges are stored to all storage capacitors structured between the capacitor lines CL and pixel electrodes 6 in a case that the number of the broken lines is one. Thereby, the potential during the non-selection period of all pixel electrodes 6 can be maintained.
However, according to the conventional manufacturing method, if breaking of lines occurs in the capacitor lines CL, the layer short-circuit is generated between the portion, which is beyond the broken portion of the capacitor line CL, and the data line DL. Due to this, even if no breaking of lines occurs in all gate liens GL, the manufactured TFT panel becomes a defective product having the layer short-circuit, and the manufacturing yield of TFT panel is decreased.
Moreover, the following problem existed in the conventional TFT panel manufacturing method.
That is, both gate lines GL and capacitor lines CL are short-circuited to the same oxide voltage-apply lines 8. Due to this, when the substrate 1 is cut along the cutting line B after the manufacture of the TFT panels and the oxide voltage-apply line forming portion is separated the gate lines GL and the capacitor lines CL are often short-circuited at the cut end of the substrate.
The above problem can be explained as follows.
When the substrate 1 is cut along the cutting line B, an extension is generated from the gate line GL and the cut end of the capacitor line CL. The extension is generated by drawing out the metallic film formed in the inside of the oxide film. Then, both lines GL and CL contact to each other and the extension of one line contacts the cut end surface of the other line. Due to this, these lines GL and CL are short-circuited.